Methods of manufacturing a capacitor including a cavity containing a buried layer

ABSTRACT

Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O 2 ) when initially formed.

CLAIM OF PRIORITY

This application claims priority to and is a divisional of parentapplication number 10/795,020, filed Mar. 5, 2004, which claims thebenefit of Korean Patent Application No. 2003-32885, filed May 23, 2003the disclosures of which are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to capacitors and methods of manufacturingthe same. More particularly, the present invention relates to integratedcircuit (semiconductor) device capacitors contacting an underlying metalplug and methods of manufacturing the same.

As the integration density of integrated circuit (semiconductor) deviceshas increased, the area occupied by a semiconductor device within a chiphas generally decreased. Capacitors for storing information in dynamicrandom access memory (DRAM) devices are typically required to occupysmaller areas while maintaining the same or larger capacitance asconventional capacitors. Conventionally, to increase the capacitance ofsuch a capacitor, a concave or cylindrical lower electrode may bemanufactured and a high-k dielectric layer, such as a TaO layer, may beused. When a high-k dielectric layer is used, a lower electrode may beformed of a material having a high work function, such as ruthenium (Ru)and/or platinum (Pt) to reduce leakage current between the lowerelectrode and the dielectric layer.

For a concave lower electrode, only the inward walls of a concave aregenerally used to provide capacitance. As a result, when a distancebetween the inward walls of the concave becomes narrower with areduction in a device design rule, depositing a dielectric layertypically becomes more difficult. As a result, the concave lowerelectrode may be inadequate for highly integrated memory devices.

Although a cylindrical lower electrode may advantageously providecapacitance not only with the inward walls but also with the outwardwalls thereof, depositing a dielectric layer in such a structure maystill be difficult with a reduction in an associated design rule. Thecylindrical structure may also be unstable.

As a result of these limitations, a stack-type lower electrode may beused as will be described with reference to FIG. 1. As shown in FIG. 1,an interlayer dielectric (ILD) 15 is formed on an integrated circuit(semiconductor) substrate 10 where, for example, a metal oxidesemiconductor (MOS) transistor is formed. A plug 20 is formed in the ILD15 so as to electrically contact one of the junctions of the MOStransistor, for example, a source region of the transistor. The plug maybe formed of TiN, which will generally not react with a subsequentlyformed noble metal lower electrode.

A stack-type lower electrode 25 is formed contacting the TiN plug 20.The lower electrode 25 may be formed of a noble metal such as Ruthenium(Ru). The lower electrode 25 may be formed using chemical vapordeposition (CVD) by supplying a Ru source and an O₂ reactant gas.Subsequently, an electrode thermal treatment (or a preprocessing) may becarried out, for example, at a temperature of about 600° C. to limit orprevent transformation of the lower electrode 25.

As shown in FIG. 1, a dielectric layer, for example, a TaO layer 30, isdeposited on the surface of the lower electrode over the ILD 15. The TaOlayer 30 can be deposited using CVD by supplying a Ta source and an O₂reactant source. The TaO layer 30 may be deposited in an O₂ atmosphere,which may improve dielectric characteristics thereof. The TaO layer maybe thermally treated to improve its dielectric constant. An upperelectrode 35 is formed on the TaO layer to complete a capacitor 40.

A conventional capacitor, such as illustrated in FIG. 1, generally hasvarious limitations. The formation of the Ru lower electrode using CVDgenerally needs O₂ and the deposition of the TaO layer 30 also generallyrequires a large amount of O₂. Although it is possible to manufacture alower electrode using physical vapor deposition (PVD), which generallydoes not require O₂, highly integrated memory devices are generallyformed using CVD because the PVD process may degrade step coveragecharacteristics. Where the lower electrode 25 is formed using CVD, alarge amount of O₂ is typically solid-dissolved in the lower electrode25 and the TaO layer 30 and then diffuses to the outside, especially,toward the TiN plug 20. As a result, the surface of the TiN plug 20 maybe oxidized and a TiO₂ layer 50 may be formed at an interface betweenthe Ru lower electrode 25 and the TiN plug 20. Due to the unwanted TiO₂layer, lifting may occur between the lower electrode 25 and the TiN plug20 and contact resistance may increase, which may result in failures.

FIG. 2 is a graph of measurement results showing contact resistance ofthe TiN plug 20 before and after the TaO layer is thermally treated. Asshown in FIG. 2, before the thermal treatment, contact resistancebetween the lower electrode 25 and the TiN plug 20 is about 10² to 10⁴ohms/number of contacts (Ω/cnt, where cnt is contact area)(whichtypically depends on the diameter of the contact), which is relativelylow. However, as the thermal treatment was provided, the contactresistance is significantly increased to be about 10⁹ Ω/cnt. The thermaltreatment may be, for example, a preprocessing of the lower electrodeperformed before deposition of a dielectric layer.

Furthermore, when a stack-type lower electrode is formed of Ru, O₂contained in the Ru layer generally diffuses into the surface of theelectrode as well as the TiN plug 20 while the TaO layer 30 is thermallytreated and during other subsequent thermal treatments. As a result, thesurface of the lower electrode may suffer agglomeration, which mayadversely transform the lower electrode.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide capacitors including anintegrated circuit substrate and an interlayer dielectric disposed onthe integrated circuit substrate and including a metal plug therein. Alower electrode is disposed on the interlayer dielectric and contactingthe metal plug. The lower electrode includes a cavity therein and aburied layer in the cavity. The buried layer is an oxygen absorbingmaterial. A dielectric layer is disposed on the lower electrode and anupper electrode is disposed on the dielectric layer. The lower electrodemay be a layer of a noble metal. The buried layer may fill in the cavityand may not contain oxygen (O₂) when initially formed.

In other embodiments of the present invention, the metal plug istitanium nitride (TiN). The noble metal layer may be ruthenium (Ru),platinum (Pt), iridium (fr), osmium (Os), palladium (Pd), tungsten (W)and/or cobalt (Co). The buried layer may be a material that is etchresistant to etch chemicals used to etch silicon oxide. The buried layermay be tantalum oxide (TaO), titanium dioxide (TiO₂), silicon nitride(SiN) and/or silicon (Si).

In further embodiments of the present invention, an oxygen barrier layeris interposed between the noble metal layer and the buried layer. Theoxygen barrier layer may be a material having an oxidativecharacteristic greater than the oxidative characteristic of the metalplug. The oxygen barrier layer may be titanium (Ti), titanium richtitanium nitride (Ti-rich TiN), aluminum (Al), tungsten (W) and/ortantalum nitride (TaN).

In other embodiments of the present invention, the upper electrodeextends along the interlayer dielectric beyond a region including thelower electrode. An etch stopper is interposed between the upperelectrode and the interlayer dielectric.

In further embodiments of the present invention, capacitors are providedincluding an integrated circuit substrate and an interlayer dielectricdisposed on the integrated circuit substrate and including a metal plugtherein. A lower electrode is disposed on the interlayer dielectric andcontacting the metal plug. The lower electrode includes a noble metallayer having a cavity therein, a buried layer filled in the cavity andan oxygen barrier layer interposed between the noble metal layer and theburied layer. A dielectric layer is disposed on the lower electrode andan upper electrode disposed on the dielectric layer. The buried layer isa material layer which does not contain oxygen (O₂) and which is capableof absorbing additional O₂ and the oxygen barrier layer is a materiallayer having a better oxidative characteristic than the oxidativecharacteristic of the metal plug.

In other embodiments of the present invention, methods are provided ofmanufacturing a capacitor. An interlayer dielectric is formed on anintegrated circuit substrate and a metal plug is formed in theinterlayer dielectric. A lower electrode is formed electricallycontacting the metal plug, including forming a conductive layerincluding a cavity and electrically contacting the metal plug andforming a buried layer in the cavity. A dielectric layer is formed onthe lower electrode and an upper electrode is formed on the dielectriclayer. The buried layer may be formed of a material that is etchresistant to etch chemicals used to etch silicon oxide and theconductive layer may be a noble metal layer. The buried layer may be anoxygen absorbing material.

In further embodiments of the present invention, forming the lowerelectrode includes sequentially stacking an etch stopper and a moldoxide layer on the-interlayer dielectric in a region where the metalplug is formed. Portions of the mold oxide layer and the etch stopperare etched until the metal plug and a region adjacent to the metal plugare exposed to define a lower electrode region. A noble metal layer isdeposited on the mold oxide layer, including defining a cavity region inthe lower electrode region. A buried layer is deposited on the noblemetal layer in the cavity region in the lower electrode region. Theburied layer has a different etch rate than that of the mold oxidelayer. The buried layer and the noble metal layer are planarized untilthe mold oxide layer is exposed and the mold oxide layer is removed.

The noble metal layer may be ruthenium (Ru), platinum (Pt), iridium(Ir), osmium (Os), palladium (Pd), tungsten (W) and/or cobalt (Co). Theburied layer may be tantalum oxide (TaO), titanium dioxide (TiO₂),silicon nitride (SiN) and/or silicon (Si), wherein the SiN and Si arefree of oxygen (O₂) when formed. The buried layer may be formed bydepositing a titanium oxide (TaO) layer in a nitrogen (N₂) atmosphere.

In other embodiments of the present invention, an oxygen barrier layeris formed on the noble metal layer before forming the buried layer.Forming the oxygen barrier layer may include forming the oxygen barrierlayer of a material having an oxidative characteristic greater than theoxidative characteristic of the metal plug. The oxygen barrier layer maybe formed layer from titanium (Ti), titanium rich titanium nitride(Ti-rich TiN), aluminum (Al), tungsten (W) and/or tantalum nitride(TaN).

In further embodiments of the present invention, removing the mold oxidelayer includes removing the mold oxide layer using etch chemicals usedto etch silicon oxide. The method may further include thermally treatingthe lower electrode before forming-the dielectric layer. Thermallytreating the lower electrode may include thermally treating the lowerelectrode in an inert gas atmosphere at a temperature of from about 400°C. to about 750° C.

In other embodiments of the present invention, forming the dielectriclayer includes depositing a tantalum oxide (TaO) layer on the lowerelectrode in an oxygen (O₂) atmosphere and thermally treating the TaOlayer to crystallize a portion of the TaO layer. Thermally treating theTaO layer may include thermally treating the TaO layer in a nitrogen(N₂) atmosphere at a temperature of from about 600° C. to about 700° C.

In further embodiments of the present invention, manufacturing acapacitor includes forming an interlayer dielectric on a semiconductorsubstrate and forming a metal plug in a predetermined portion of theinterlayer dielectric. An etch stopper and a mold oxide layer are formedon the interlayer dielectric. A lower electrode region is formedincluding etching the mold oxide layer and the etch stopper until themetal plug and a region adjacent to the metal plug are exposed. A noblemetal layer, an oxygen barrier layer and a buried layer are sequentiallystacked on the mold oxide layer in the lower electrode region. The lowerelectrode region is filled by planarizing the buried layer, the oxygenbarrier layer and the noble metal layer. The mold oxide layer is removedto define a lower electrode. A dielectric layer is formed on the lowerelectrode and an upper electrode is formed on the dielectric layer.

In other embodiments of the present invention, manufacturing a capacitorincludes forming an interlayer dielectric on a semiconductor substrateand forming a metal plug in a predetermined portion of the interlayerdielectric. An etch stopper and a mold oxide layer are formed on theinterlayer dielectric. A lower electrode region is formed by etching themold oxide layer and the etch stopper until the metal plug and a regionadjacent to the metal plug are exposed. A noble metal layer, an oxygenbarrier layer and a buried layer are sequentially stacked on the moldoxide layer. The lower electrode region is filled by planarizing theburied layer, the oxygen barrier layer and the noble metal layer todefine a resultant structure. The resultant structure is thermallytreated and then the mold oxide layer and the buried layer are removed.The oxygen barrier layer is removed to define a lower electrode. Adielectric layer is formed on the lower electrode and an upper electrodeis formed on the dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing embodiments thereof withreference to the attached drawings in which:

FIG. 1 is a cross-sectional illustration of a capacitor including aconventional stack-type lower electrode;

FIG. 2 is a graph illustrating contact resistance of a TiN plug beforeand after thermal treatment;

FIG. 3 is a cross-sectional view illustrating a capacitor according tosome embodiments of the present invention;

FIGS. 4A through 4C are cross-sectional views illustrating methods ofmanufacturing the capacitor of FIG. 3 according to some embodiments ofthe present invention;

FIGS. 5 and 6 are graphs of Auger electron spectroscopy (AES) resultsillustrating oxygen distributions in a lower electrode and a TiN plugbefore and after thermal treatment;

FIG. 7 is a graph illustrating contact resistance of a TiN plug ofwafers where lower electrodes are formed under various conditions;

FIG. 8 is a cross-sectional view illustrating a capacitor according tosome other embodiments of the present invention; and

FIGS. 9A through 9C are cross-sectional views illustrating methods ofmanufacturing the capacitor of FIG. 8 according to further embodimentsof the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the relative sizes of regions may be exaggerated for clarity.It will be understood that when an element is referred to as being“attached”, “connected” or “coupled” to another element, it can bedirectly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly attached,” “directly connected” or “directly coupled” toanother element, there are no intervening elements present. Like numbersrefer to like elements throughout the specification. As used herein theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother elements as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in the Figures is turned over, elements describedas being on the “lower” side of other elements would then be oriented on“upper” sides of the other elements. The exemplary term “lower”, cantherefore, encompasses both an orientation of “lower” and “upper,”depending of the particular orientation of the figure.

FIG. 3 is a cross-sectional illustration of a capacitor according tosome embodiments of the present invention. FIGS. 4A through 4C arecross-sectional views illustrating methods of manufacturing thecapacitor of FIG. 3 according to some embodiments of the presentinvention.

As shown in the embodiments of FIG. 3, an ILD 105 is disposed on anintegrated circuit (semiconductor) substrate 100. The semiconductorsubstrate 100 may include, for example, a MOS transistor (including agate, a source, and a drain), a bit line, and connection pads disposedin an upper portion of the semiconductor substrate 100.

A plug 110 is positioned in the ILD 105, for example, to provide anelectrical connection to the source. The plug 110 may be formed of ametal material, which is highly conductive and may improve contactcharacteristics between the plug 110 and a noble metal lower electrodeto be formed on the plug 110 as will be described later herein. Aconventional plug is typically formed of doped polysilicon, which mayhave a high resistance and may cause a silicidation with a noble metalof the lower electrode, which in turn may lead to volume expansion. As aresult, lifting may occur at the contact between the plug 110 and thelower electrode. In some embodiments of the present invention, the plug110 for connecting the lower electrode and the source (or a connectionpad connected to the source) is formed of TiN, which is highlyconductive and generally has a minimal reaction with the lower electrodematerial.

As shown in the embodiments of FIG. 3, a lower electrode 145 is disposedon the ILD 105 contacting the plug 110. The lower electrode 145 shown inFIG. 3 includes a Ru layer 130 that includes a cavity, a buried layer140 filled in the cavity, and an oxygen barrier layer 135 interposedbetween the Ru layer 130 and the buried layer 140.

The Ru layer 130 functions as an electrode in the structure of the lowerelectrode 145. In other embodiments of the present invention, instead ofthe Ru layer 130, a layer formed of one or more of the other noblemetals, such as Pt, Ir, Os, Pd, W, and/or Co, may be used.

The buried layer 140 is filled in the cavity included in the Ru layer130. In some embodiments of the present invention, the buried layer 140is formed of a material that is not removed by etch chemicals used forremoving silicon oxide but which can be oxidized. In particular, theburied layer 140 may be formed of a material that can absorb additionaloxygen. The buried layer 140 can be formed, for example, of one or morematerial such as, for example, TaO, TiO₂, SiN, and/or Si. In particularembodiments as illustrated in FIG. 3, a TaO layer, which lacks O₂, maybe used.

The oxygen barrier layer 135 may be formed of a material having a betteroxidative characteristic than the TiN plug 110. For example, the oxygenbarrier layer 135 may be formed of one or more of Ti, Ti-rich TiN, Al,W, and/or TaN.

An etch stopper 115 may be provided that covers the ILD 105 on bothsides of the lower electrode 145 and protects the ILD 105. As shown inthe embodiments of FIG. 3, a TaO layer 155 is coated as a dielectriclayer on the lower electrode. The TaO layer 155 may be partially orwholly crystallized to provide a high dielectric constant. An upperelectrode 150 is disposed on the TaO layer 155 to complete a capacitor165 in the embodiments of FIG. 3. The upper electrode 150 may be formed,for example, of a noble metal layer.

Methods of manufacturing the capacitor of FIG. 3 will now be describedwith reference to FIGS. 4A through 4C. As shown in FIG. 4A, an ILD 105is deposited on an integrated circuit (semiconductor) substrate 100including a MOS transistor, a bit line and connection pads formedthereon. The ILD 105 can be formed of a silicon oxide layer. The formedILD 105 may be etched until a source of the MOS transistor or aconnection pad connected to the source is exposed, thereby forming acontact hole. A TiN layer may then be deposited on the ILD 105 to fillthe contact hole and planarized, for example, by chemical mechanicalpolishing (CMP) or an etchback process, to form a TiN plug 110 in theILD 105.

For the embodiments shown in FIG. 4A-4C, an etch stopper 115 and a moldoxide layer 120 are sequentially stacked on the ILD 105 in the regionwhere the TiN plug 110 is formed. The etch stopper 115, which may beused to protect the ILD 105, may be formed of a material having adifferent etch rate (with respect to a particular reference etchchemistry) than that of the ILD 105, for example, silicon nitride (SiN).The mold oxide layer 120 may be, for example, a tetraethoxysilane (TEOS)layer or a spin on glass (SOG) layer, which can typically be easilyremoved later. The mold oxide layer 120 and the etch stopper 115 maythen be selectively etched until the region where the plug 110 is formedis exposed to define a lower electrode region 125.

Referring now to the embodiments illustrated in FIG. 4B, a noble metallayer, such as a Ru layer 130, is deposited contacting the exposed plug110. The Ru layer 130 may be formed using CVD by supplying a Ru sourceand an O₂ source, which may provide an improved step coverage. The Rulayer 130 may be formed to a thickness of, for example, about 200 Å to500 Å.

For the illustrated embodiments, an oxygen barrier layer 135 isdeposited on the Ru layer 130. The oxygen barrier layer 135 may beformed of a material having a better oxidative characteristic than theplug 110, for example, one or more of Ti, Ti-rich TiN, Al, W, and/orTaN, as described above. The oxygen barrier layer 135 may be formed, forexample, to a thickness of about 50 Å to 200 Å using CVD.

A buried layer 140 is formed on the oxygen barrier layer 135 so as tofill the lower electrode region 125. The buried layer 140 in someembodiments of the present invention is formed of a material that isresistant to being removed by etch chemicals used for removing siliconoxide, in other words, a material having a different etch rate (withrespect to a particular reference etch chemistry) than that of the moldoxide layer 120, which is also capable of absorbing additional oxygen.For example, the buried layer can be formed of one or more of TaO, TiO₂,SiN, and/or Si. In the illustrated embodiments of FIGS. 4A-4C, a TaOlayer, which lacks O₂, is deposited in a N₂ atmosphere.

Referring now to the embodiments of FIG. 4C, the buried layer 140, theoxygen barrier layer 135 and the Ru layer 130 are planarized using, forexample, CMP or an etchback process, until the surface of the mold oxidelayer 120 is exposed to form a stack-type lower electrode filled in thelower electrode region 125 (shown in FIG. 4A). The-mold oxide layer 120is removed, for example, using etch chemicals used for removing siliconoxide, such as a HF-containing solution. The buried layer 140, which isdisposed within the lower electrode region 125, is not significantlyremoved by the etch chemicals used for removing silicon oxide. Thus, thestack-type lower electrode 145 and the etch stopper 115, disposed onboth sides of the lower electrode 145, remain on the ILD 105. The ILD105, which may be formed of a SiO₂-related compound, is protected by theetch stopper 115 from the etch chemicals used for removing siliconoxide.

Referring again to FIG. 3 and FIG. 4B, before a dielectric layer isformed, the resultant lower electrode structure may be pre-processed inan inert gas atmosphere, for example, a N₂ atmosphere, at a temperatureof about 400° C. to 750° C., which may reduce or prevent transformationof the lower electrode 145. This preprocessing typically causes grainsto grow in the Ru layer 130 constituting the lower electrode 145 to makethe Ru layer 130 dense. As a result, penetration of oxygen may bereduced or prevented during the subsequent deposition of the dielectriclayer.

After such a preprocessing, a TaO layer 155 may be deposited as adielectric layer on the surface of the lower electrode 145. The TaOlayer 155 may be deposited in an O₂ atmosphere, which may improve itsdielectric characteristics. After the TaO layer 155 is deposited, it maybe thermally treated at a temperature of about 600° C. to 700° C., whichmay further improve its dielectric characteristics. Immediately afterthe deposition, the TaO layer 155 is typically in an amorphous state andhas a low dielectric constant. Once a thermal treatment is carried outat a temperature of about 600° C. to 700° C., the TaO layer 155 may bepartially or wholly crystallized and have an improved dielectricconstant. The thermal treatment may be carried out in a N₂ atmosphere,which may reduce or prevent additional penetration of oxygen.

A noble metal layer may be deposited on the dielectric TaO layer 155 andthen patterned to a predetermined portion, to form an upper electrode150. Thus, a capacitor 160 may be formed. The capacitor 160 of someembodiments of the present invention includes an oxygen barrier layer135, which is oxidized faster than the TiN plug 110 included in thelower electrode 145. The oxygen barrier layer 135 may reduce or preventdiffusion of oxygen contained in the Ru layer 130 and/or the TaO layer155 toward the TiN plug 110 in a subsequent thermal treatment. In otherwords as the oxygen barrier layer 135 generally has a better oxidativecharacteristic than the TiN plug 110, it absorbs oxygen diffused towardthe TiN plug 110 during the thermal treatment.

The buried layer 140, which is capable of oxidation as described above,may also absorb oxygen contained in the Ru layer 130 and the TaO layer155. Thus, as most of oxygen contained in the Ru layer 130 and the TaOlayer 155 may be absorbed in the oxygen barrier layer 135 and the buriedlayer 140, diffusion of oxygen into the TiN plug 110 can be reduced oreven prevented.

FIGS. 5 and 6 are graphs of Auger electron spectroscopy (AES) resultsshowing oxygen distributions in a lower electrode and a TiN plug beforeand after thermal treatment. AES analysis is a method of sputtering alayer using predetermined atoms to analyze elements of the-layer throughthe emitted elements.

FIG. 5 is a graph of results obtained when the AES analysis is performedwithout preprocessing after the lower electrode 145 is completed. Oxygenatoms are distributed at an interface between the TiN plug 110 and theRu layer 130, in the Ru layer 130 and at an interface between the Rulayer 130 and the oxygen barrier layer 135.

Thereafter, the lower electrode is thermally treated at a temperature ofabout 650° C. to 750° C. As a result, as shown in FIG. 6, while theoxygen atoms move into the oxygen barrier layer 135, which has arelatively good oxidative characteristic, they do not exist at theinterface between the TiN plug 110 and the Ru layer 130. Consequently,it is observed that, after the thermal treatment, most of the oxygenatoms contained in the Ru layer 130 move into the oxygen barrier layer135 and the surface of the TiN plug 110 is not significantly oxidized.

FIG. 7 is a graph showing contact resistances of TiN plugs of each waferwhere lower electrodes are formed under various conditions. In FIG. 7,the x-axis represents reference wafer numbers (Nos.). In wafer No. 02, aRu layer is deposited using physical vapor deposition (PVD) withoutsupply of oxygen, and, in wafer No. 06, a Ru layer is deposited usingCVD and a preprocessing is performed. In wafer No. 08, providedaccording to some embodiments of the present invention, a Ru layer isdeposited using CVD, a Ti-rich TiN oxygen barrier layer is formed, a TaOburied layer is formed and a preprocessing is performed. In wafer No.10, also provided according to some embodiments of the presentinvention, a Ru layer is deposited using CVD, a Ti-rich TiN oxygenbarrier layer is formed and then a TaO buried layer is formed.Thereafter, a preprocessing is performed, a TaO dielectric layer isformed and the dielectric layer is thermally treated.

In the case of wafer No. 6, when the Ru layer is formed using CVD andthen the preprocessing is performed, the surface of the TiN plug isoxidized such that resistance increases to be 10⁸ Ω/cnt or higher.However, when the oxygen barrier layer 135 is formed according to someembodiments of the present invention as shown in the cases of wafer Nos.8 and 9, contact resistance is as low as 1000 Ω/cnt or lower, and thisresult is similar to when a Ru layer is formed using PVD.

FIG. 8 is a cross-sectional view illustrating a capacitor according tofurther embodiments of the present invention. In the illustratedembodiments of FIG. 8, the same reference numerals as in the embodimentsof FIG. 3 are used to denote the corresponding elements, and adescription thereof will not be repeated here.

As shown in the embodiments of FIG. 8, a lower electrode 146 includes aRu layer 130 including a cavity and a buried layer 140 that is filled inthe Ru layer 130. As described with reference to the embodiments of FIG.3, another noble metal layer can be used instead of the Ru layer 130.Also, the buried layer 140 may be formed of a material that is notsignificantly removed by etch chemicals used for removing silicon oxide,such as a material having a different etch rate than that of the moldoxide layer 120 and which is capable of absorbing additional oxygen. Theburied layer 140 can be formed of, for example, one or more of TaO,TiO₂, SiN, and/or Si. More particularly, the buried layer 140 may be ofa TaO layer that may be deposited in a N₂ atmosphere in suchembodiments. The dielectric layer and the upper electrode may be thesame as in the embodiments of FIG. 3.

Methods of manufacturing the capacitor of FIG. 8 according someembodiments of the present invention will now be-described. Initially, aRu layer 130 and a buried layer 140 may be sequentially stacked on theresultant structure shown in FIG. 4A. The buried layer 140 and the Rulayer 130 may be planarized until the surface of the mold oxide layer120 is exposed and then the mold oxide layer 120 may be removed usingetch chemicals, thereby completing a lower electrode 146 (FIG. 8).

As described with reference to FIG. 3 and FIGS. 4A-4C, a preprocessingof the lower electrode 146, formation of a dielectric layer, a thermaltreatment of the dielectric layer and formation of an upper electrodemay be sequentially carried out. For the embodiments of FIG. 8, afterthe thermal treatment, oxygen atoms contained in the Ru layer 130 andthe dielectric layer may be absorbed into the buried layer 140 anddiffusion of oxygen into the plug 110 can be reduced or prevented.

FIGS. 9A through 9C are cross-sectional views illustrating methods ofmanufacturing the capacitor of FIG. 8. In FIGS. 9A-9C, the samereference numerals as FIGS. 3 and 4A-4C are used to denote correspondingelements and a description thereof will not be repeated here. Also, asformation of an ILD 105 through formation of an oxygen barrier layer 135as shown in FIG. 4A may be the same as described previously, onlysubsequent processes will be further described.

Referring now to the embodiments illustrated in FIG. 9A, a buried layer142 is formed on the oxygen barrier layer 135 to fill the lowerelectrode region 125. As described previously, the oxygen barrier layer135 may be formed of a material having a better oxidative characteristicthan a TiN plug 110, such as one or more of Ti, Ti-rich TiN, Al, W,and/or TaN. As used herein, a Ti-rich layer has a higher concentrationof Ti than the corresponding TiN plug 110. The buried layer 142 may beformed of a material that is easily removed by etch chemicals, forexample, a material having the same etch rate as that of a material forthe mold oxide layer 120.

As shown in FIG. 9B, the buried layer 142, the oxygen barrier layer 135and the Ru layer 130 may be planarized using CMP or an etchback processuntil the surface of the mold oxide layer 120 is exposed. Thereafter,the resultant structure of the integrated circuit (semiconductor)substrate 100 may be thermally treated in an inert gas atmosphere, forexample, in a N₂ atmosphere, which may reduce or prevent transformationof the Ru layer 130. As a result, oxygen atoms contained in the Ru layer130 can diffuse to the outside. However, as the oxygen barrier layer135, which has a better oxidative characteristic than the TiN plug 110,is formed on the Ru layer 130, most of oxygen atoms contained in the Rulayer 130 may be absorbed at the oxygen barrier layer 135. Thus,diffusion of oxygen into the TiN plug 110 may be reduced or prevented,thereby protecting the TiN plug 110 from oxidation.

As shown in FIG. 9C, the resultant structure may be dipped in etchchemicals for removing the silicon oxide layer to remove the mold oxidelayer 120 and the buried layer 142 having little selectivity withrespect to the mold oxide layer 120. Then, the oxygen barrier layer 135remaining on the Ru layer 130 may be removed to form a cylindrical lowerelectrode 131. In addition, a capacitor dielectric layer may be formedon the cylindrical lower electrode and an upper electrode may be formedon the capacitor dielectric layer.

In the embodiments of FIGS. 8 and 9A-9C, the oxygen barrier layer 135and the buried layer 142 are formed on the Ru layer 130. Also, oxygencontained in the Ru layer 130 may be exhausted at the oxygen barrierlayer 135 while an electrode is thermally treated, and then the oxygenbarrier layer 135 and the buried layer 142 may be removed to form thecylindrical electrode.

As described above for some embodiments of the present invention, alower electrode may comprise a noble metal layer having a cavity, aburied layer filling the cavity and/or an oxygen barrier layerinterposed between the noble metal and the buried layer. The buriedlayer may be formed of a material capable of absorbing additional oxygenand which is not significantly removed by etch chemicals used to removeoxide, whereas the oxygen barrier layer may be formed of a materialhaving a better oxidative characteristic than a metal plug contactingthe lower electrode.

Thus, in such embodiments, during a subsequent thermal treatment, mostof oxygen atoms remaining in the noble metal layer and the dielectriclayer may be absorbed on the oxygen barrier layer, which has a betteroxidative characteristic than the metal plug. Oxygen atoms may also beabsorbed into the buried layer. Therefore, diffusion of oxygen towardthe plug may be reduced or prevented, which may protect the plug fromoxidation. As a result, contact resistance between the plug and thelower electrode may be reduced so that electrical characteristics of acapacitor can be improved.

The present invention has been described in an illustrative manner, andit is to be understood that the terminology used is intended to be inthe nature of description rather than of limitation. Many modificationsand variations of the present invention are possible in light of theabove teachings. Therefore, it is to be understood that within the scopeof the appended claims, the invention may be practiced otherwise than asspecifically described.

1. A method of manufacturing a capacitor, the method comprising: forming an interlayer dielectric on an integrated circuit substrate; forming a metal plug in the interlayer dielectric; forming a lower electrode electrically contacting the metal plug, including forming a conductive layer including a cavity and electrically contacting the metal plug and forming a buried layer in the cavity; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.
 2. The method of claim 1 wherein forming a lower electrode includes forming the buried layer of a material that is etch resistant to etch chemicals used to etch silicon oxide and wherein forming a conductive layer comprises forming a noble metal layer.
 3. The method of claim 1 wherein forming a lower electrode includes forming the buried layer being capable of absorbing additional oxygen (O₂) and wherein forming a conductive layer comprises forming a noble metal layer.
 4. The method of claim 1 wherein forming the lower electrode comprises: sequentially stacking an etch stopper and a mold oxide layer on the interlayer dielectric in a region where the metal plug is formed; etching portions of the mold oxide layer and the etch stopper until the metal plug and a region adjacent to the metal plug are exposed to define a lower electrode region; depositing a noble metal layer on the mold oxide layer, including defining a cavity region in the lower electrode region; depositing a buried layer on the noble metal layer in the cavity region in the lower electrode region, the buried layer having a different etch rate than that of the mold oxide layer; planarizing the buried layer and the noble metal layer until the mold oxide layer is exposed; and removing the mold oxide layer.
 5. The method of claim 4 wherein the noble metal layer comprises ruthenium (Ru), platinum (Pt), iridium (fr), osmium (Os), palladium (Pd), tungsten (W) and/or cobalt (Co).
 6. The method of claim 4 wherein forming the buried layer comprises forming the buried layer from tantalum oxide (TaO), titanium dioxide (TiO₂), silicon nitride (SiN) and/or silicon (Si), which lacks oxygen.
 7. The method of claim 6 wherein forming the buried layer comprises depositing a titanium oxide (TaO) layer in a nitrogen (N₂) atmosphere.
 8. The method of claim 4 further comprising forming an oxygen barrier layer on the noble metal layer before forming the buried layer.
 9. The method of claim 8 wherein forming the oxygen barrier layer comprises forming the oxygen barrier layer of a material having an oxidative characteristic greater than the oxidative characteristic of the metal plug.
 10. The method of claim 8 wherein forming the oxygen barrier layer comprises forming the oxygen barrier layer from titanium (Ti), titanium rich titanium nitride (Ti-rich TiN), aluminum (Al), tungsten (W) and/or tantalum nitride (TaN).
 11. The method of claim 4 wherein removing the mold oxide layer comprises moving the mold oxide layer using etch chemicals used to etch silicon oxide.
 12. The method of claim 4 further comprising thermally treating the lower electrode before forming the dielectric layer.
 13. The method of claim 12 wherein thermal treating the lower electrode comprises thermal treating the lower electrode in an inert gas atmosphere at a temperature of from about 400° C. to about 750° C.
 14. The method of claim 4 wherein forming the dielectric layer comprises: depositing a tantalum oxide (TaO) layer on the lower electrode in an oxygen (O₂) atmosphere; and thermally treating the TaO layer to crystallize a portion of the TaO layer.
 15. The method of claim 14 wherein thermally treating the TaO layer comprises thermally treating the TaO layer in a nitrogen (N₂) atmosphere at a temperature of from about 600° C. to about 700° C.
 16. The method of claim 1 wherein forming a lower electrode further comprises forming an oxygen barrier layer between the buried layer and the conductive layer.
 17. A method of manufacturing a capacitor, the method comprising: forming an interlayer dielectric on a semiconductor substrate; forming a metal plug in a predetermined portion of the interlayer dielectric; forming an etch stopper and a mold oxide layer on the interlayer dielectric; forming a lower electrode region including etching the mold oxide layer and the etch stopper until the metal plug and a region adjacent to the metal plug are exposed; sequentially stacking a noble metal layer, an oxygen barrier layer and a buried layer on the mold oxide layer in the lower electrode region; filling the lower electrode region by planarizing the buried layer, the oxygen barrier layer and the noble metal layer; removing the mold oxide layer to define a lower electrode; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer.
 18. A method of manufacturing a capacitor, the method comprising: forming an interlayer dielectric on a semiconductor substrate; forming a metal plug in a predetermined portion of the interlayer dielectric; forming an etch stopper and a mold oxide layer on the interlayer dielectric; forming a lower electrode region by etching the mold oxide layer and the etch stopper until the metal plug and a region adjacent to the metal plug are exposed; sequentially stacking a noble metal layer, an oxygen barrier layer and a buried layer on the mold oxide layer; filling the lower electrode region by planarizing the buried layer, the oxygen barrier layer and the noble metal layer to define a resultant structure; thermally treating the resultant structure; removing the mold oxide layer and the buried layer; removing the oxygen barrier layer to define a lower electrode; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer. 